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fractional - n/integer - n pll synthesizer data sheet adf4151 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third p arties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their resp ective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rig hts reserved. f eatures fractional - n synthesizer and integer - n synthesizer rf bandwidth to 3 .5 ghz 3.0 v to 3.6 v power supply 1.8 v logic compatibility separate charge pump supply (v p ) allows extended tuning voltage ( up to 5 .5 v ) in 3 v systems programmable dual - modulu s prescaler of 4/5 or 8/9 programmable rf output phase 3 - wire serial interface analog and digital lock detect switched bandwidth fast lock mode cycle slip reduction a pplications wireless infrastructure (w - cdma, td - scdma, wimax, gsm, pcs, dcs, dect) t est eq uipment wireless lans, catv equipment clock g eneration g eneral d escription the adf4151 allows implementation of fractional - n or integer - n phase - locked loop (pll) frequency synthesizer s if used with an extern al voltage controlled oscillator (vco), loop filter , an d external reference frequency. the adf4151 is used with external vco parts and is footprint an d softwar e co mpatible with the adf4350 . the part consists of a low noise digital phase frequency detector (pfd), a precision charge pump, and a programmable reference divider. there is a - based fractional interpolator to allow programmable fractional - n division. the int, frac, and mod registers define an overall n divider [n = (int + (frac/mod))] . the rf output phase is programmable for applications that require a particular phase relationship between the output and the reference. the adf4151 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter. control of all the on - chip registers is through a simple 3 - wire interface. the device operates with a power supply ranging from 3.0 v to 3.6 v that can be powered down when not in use. the adf4151 is available in a 5 mm 5 mm package. f unctional block d iagram muxout cp out ld sw ref in clk data le av dd x sdv dd dv dd v p a gnd ce cp gnd sd gnd d gnd r set rf in + rf in ? phase comparator fl o switch charge pump 10-bit r counter 2 divider 2 doubler function latch data register integer reg n counter fraction reg third-order fractional interpolator modulus reg multiplexer lock detect adf4151 10265-001 figure 1.
adf4151 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 transistor count ........................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 circuit description ......................................................................... 11 reference input section ............................................................. 11 rf n divider ............................................................................... 11 int, frac, mod, and r c ounter relationship .................... 11 int n mode ................................................................................ 11 r counter .................................................................................... 11 phase frequenc y detector (pfd) and charge pump ............ 11 muxout and lock detect ...................................................... 12 input shift registers ................................................................... 12 program modes .......................................................................... 12 register maps .............................................................................. 13 register 0 ..................................................................................... 17 register 1 ..................................................................................... 17 register 2 ..................................................................................... 17 register 3 ..................................................................................... 19 register 4 ..................................................................................... 19 register 5 ..................................................................................... 19 initialization sequence .............................................................. 19 rf synthesizer a worked example ...................................... 20 modulus ....................................................................................... 20 reference doubler and reference divider ............................. 20 12- bit programmable modulus ................................................ 20 cycle slip reduction for faster lock times ........................... 21 spurious optimization and fast lock ...................................... 21 fast lock timer and register sequences ................................ 21 fast lock an example ............................................................ 22 fast lock loop filter topology ............................................. 22 spur mechanisms ....................................................................... 22 spur consistency and fractional spur optimization ........... 23 phase resync ............................................................................... 23 applications information .............................................................. 24 direct conversion modulator .................................................. 24 interfacing ................................................................................... 25 pcb design guidelines for chip scale package .................... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 12/11 rev. a to rev. b changes to normalized 1/f noise parameter, table 1 ................. 4 11/11 rev. 0 to rev. a change s to figure 28 ...................................................................... 23 10/1 1 revision 0: initial version
data sheet adf4151 rev. b | page 3 of 28 specifications av dd = dv dd = s d vdd = 3.3 v 10%; v p = av dd to 5.5 v; a gnd = d gnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ? 40c to +85 c . table 1 . parameter b version unit conditions/comments min typ max ref in characteristics input frequency 10 250 mhz for f < 10 mhz , ensure slew rate > 21 v/s input sensitivity 0.7 av dd v p -p biased at av dd /2 1 input capacitance 10 pf input current 60 a rf input characteristics for lower frequencies, ensure slew rate > 400 v/s rf input frequency (rf in ) 0.5 3. 5 ghz ?10 dbm rf input power + 5 dbm prescaler output frequency 750 mhz m a ximum pfd frequency fractional - n mode low spur mode 26 mh z low noise mode 32 mhz integer - n mode 32 mhz charge pump i cp sink/source r set = 5.1 k ? high value 4.5 ma low value 0.281 ma r set range 2.7 10 k ? i cp leakage 1 na v cp = v p /2 sink and source matching 2 % 0.5 v v cp v p ? 0.5 v i cp vs. v cp 1.5 % 0.5 v v cp v p ? 0.5 v i cp vs. temperature 2 % v cp = v p /2 logic inputs input high voltage, v inh 1.5 v input low volta ge, v inl 0.6 v input current, i inh /i inl 1 a input capacitance, c in 5 .0 pf logic outputs output high voltage, v oh dv dd ? 0.4 v cmos output chosen output high current, i oh 500 a output low voltage, v o 0.4 v i ol = 500 a power supplies av dd 3.0 3.6 v dv dd , sd vdd av dd v p av dd 5.5 v di dd + ai dd 2 40 50 ma v p i dd 2 2 ma v p = 5 v low power sleep mode 1 a
adf4151 data sheet rev. b | page 4 of 28 parameter b version unit conditions/comments min typ max noise characteristics normalized in - band phase no ise floor (pn synth ) 3 ?221 dbc/hz pll loop bw = 500 khz (abp = 3 ns) normalized 1/f noise (pn 1_f ) 4 ?118 dbc/hz 10 khz offset. normalized to 1 ghz (abp = 3 ns) normalized in - band phase noise floor (pn synth ) 3 ?220 dbc /hz pll loop bw = 50 0 khz (abp = 6 ns); low noise mode normalized 1/f noise (pn 1_f ) 4 ?115 dbc/hz 10 khz offset; normalized to 1 ghz (abp = 6 ns); low noise mode spuriou s signals due to pfd frequency 5 ?107 dbc pfd = 25 mhz 1 ac coupling ensures av dd /2 bias. 2 t a = 25c; av dd = dv dd = 3.6 v; prescaler = 4/5; f refin = 130 mhz; f pfd = 26 mhz; f rf = 1.742 ghz. 3 the synthesizer phase noise floor is estimated by measuring the in - band phase noise at t he output of the vco and subtracting 20 log n (where n is the n divider value) and 10 log f pfd . pn synth = pn tot C 10 log f pfd C 20 log n 4 the pll phase noise is composed of 1/f (flicker) noise plus the normalized pll noise floor. the formula for calculati ng the 1/f noise contribution at an rf frequency ( f rf ) and at a frequency offset (f) is given by pn = p 1_f + 10 log(10 khz/f) + 20 log( f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll 5 spurious measured on eval - adf4151eb1z with rf buffer between vco output and rf input by - passed, using a rohde & schwarz fsup signal source analyzer.
data sheet adf4151 rev. b | page 5 of 28 timing cha racteristics av dd 1 , av dd 2 = dv dd = sd vdd = 3.3 v 10%; v p = av dd to 5.5 v; a gnd = d gnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85 c. table 2 . parameter limit (b version) unit t est conditions/comments t 1 20 ns min le s etup t ime t 2 10 ns min data to clk s etup t ime t 3 10 ns min data to clk h old t ime t 4 25 ns min cl k h igh d uration t 5 25 ns min clk l ow d uration t 6 10 ns min cl k to le s etup t ime t 7 20 ns min le p ulse w idth clk data le le db31 (msb) db30 db1 (lsb) (control bit c2) db2 (lsb) (control bit c3) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 10265-002 figure 2 . timing diagram
adf4151 data sheet rev. b | page 6 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating av dd 1, av dd 2 to gnd 1 ? 0.3 v to +3.9 v av dd 1, av dd 2 to dv dd ? 0.3 v to +0.3 v v p to av dd 1, av dd 2 ? 0.3 v to +5.8 v digital i/o voltage to gnd 1 ? 0.3 v to v dd + 0.3 v analog i/o voltage to gnd 1 ? 0.3 v to v dd + 0.3 v ref in to gnd 1 ? 0.3 v to v dd + 0.3 v operating temperature r ange ?40 c to +85 c storage temperature range ?65 c to +125 c maximum junction temperature 150 c lfcsp ja thermal impedance (paddle - soldered) 27.3 c/w reflow soldering peak temperature 260 c time at peak temperature 40 sec 1 gnd = a gnd = d gnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. transistor count 36685 (cmos) and 967 (bipolar) esd caution
data sheet adf4151 rev. b | page 7 of 28 pin configuration an d function descripti ons 1 clk 2 data 3 le 4 ce 5 sw 6 7 24 23 nc 22 21 20 19 18 17 8 sdv dd adf4151 top view (not to scale) 9 a gnd 10 11 ref in 12 d gnd 13 dv dd 14 15 16 32 31 30 29 28 sd gnd 27 26 25 pin 1 indicator v p cp out cp gnd muxout r set nc rf in + rf in ? nc nc nc d gnd ld a gnd a gnd a gnd nc av dd 2 av dd 2 av dd 1 notes 1. nc = no connect. do not connect to this pin. 2. the lfcsp has an exposed paddle that must be connected to gnd. 10265-003 fig ure 3 . pin configuration table 4 . pin function descriptions pin o. nemonic description 1 clk serial clock input. data is clocked into the 32 - bit shift register on the clk rising edge. this input is a hig h impedance cmos input. 2 data serial data input. the serial data is loaded , msb first , with the three lsbs as the control bits. this input is a high impedance cmos input. 3 le load enable, cmos input. when le goes high, the data stored in the shift regi ster is loaded into the register that is selected by the three lsbs. 4 ce chip enable. a logic low on this pin powers down the device and puts the charge pump into three - state mode. taking the pin high powers up the device depending on the status of the p ower - down bits. 5 sw fast l ock switch. make a connection to this pin from the loop filter when using the fast lock mode. 6 v p charge pump power supply. this pin should be greater than or equal to av dd . in systems where av dd x is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5.5 v. 7 cp out charge pump output. when enabled, this provides i cp to the external loop filter. the output of the loop filter is connected to v tune to drive the external vco. 8 cp gnd charge pump gro und. this is the ground return pin for cp out . 9 , 11, 18 , 21 a gnd analog ground. this is a ground return pin for av dd 1 and av dd 2. 10 av dd 1 analog power supply. this pin ranges from 3.0 v to 3.6 v. decoupling capacitors to the analog ground plane are to b e placed as close as possible to this pin. av dd must have the same value as dv dd . 12 , 13, 19, 20, 23, 24 nc no connect . do not connect to this pin. 14 rf in + input to the rf input. this small signal input is ac - coupled to the external vco. 15 rf in ? compl ementary input to the rf input. this p in must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. 16, 17 av dd 2 analog power supply. this pin ranges from 3.0 v to 3.6 v. decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. av dd x must have the same value as dv dd .
adf4151 data sheet rev. b | page 8 of 28 pin no. mnemonic description 22 r set connecting a resistor between this pin and gnd sets the charge pump output current. the nominal voltage bias at the r set pin is 0 .49 v. the relationship between i c p and r set is set cp r i 22.95 = where: r set = 5.1 k?. i cp = 4. 5 ma . 2 5 ld lock detect output pin. this pin outputs a logic high to indicate pll lock ; a logic low output indicates loss of pll lock. 2 6 , 27 d gnd digital ground. ground return path for dv dd . 28 dv dd digital power supply. this pin should be the same voltage as av dd . decoupling capacitors to the ground plane should be placed as close as possible to this pin. 2 9 ref in reference input. this is a cmos input with a nominal threshold of v dd / 2 and a dc equivalent input resistance of 100 k? . this input can be driven from a ttl or cmos crystal oscillator , or it can be ac - coupled. 30 mux out multiplexer output. this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 31 sd gnd digital sigma - delta ( - ) modulator ground. ground return path for the - modulator. 32 sdv dd power supply pin for the digital - modulator . should be the same voltage as av dd x . decoupling capacitors to the ground plane are to be placed as clos e as possible to this pin. ep the exposed pad must be connected to gnd .
data sheet adf4151 rev. b | page 9 of 28 typical performance characteristics 0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 power (dbm) frequency (ghz) ?40c +25c +85c 10265-004 figure 4 . rf input sensitivity 6.0 ?6.0 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.0 4.5 4.0 i cp (ma) v cp (v) 0.28ma 0.28ma 0.56ma 0.56ma 1.13ma 1.13ma 2.25ma 2.25ma 4.5ma 4.5ma source sink 10265-005 figure 5. charge pump output characteristics, v p = 5 v, s elected i cp v alues b etween 0.28 ma ( m in) and 4.5 ma (m ax) , r set = 5.1 k? ?90 ?100 ?99 ?98 ?97 ?96 ?95 ?94 ?93 ?92 ?91 2.60 2.61 2.62 2.63 2.64 2.65 2.66 2.67 2.68 2.70 2.69 phase noise (dbc/hz) frequency (ghz) low noise mode low spur mode 10265-006 figure 6 . in - band phase noise measured at 10 khz offset for low noise mode and low spur mode, pfd = 25 mhz, pll loop bandwidth = 50 khz 6.0 ?6.0 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.0 4.5 4.0 i cp mismatch (%) v cp (v) i cp = 0.28ma i cp = 0.56ma i cp = 1.13ma i cp = 2.25ma i cp = 4.5ma 10265-007 figure 7 . charge pump output mismatch vs. v cp , s e lected i cp v alues b etween 0.28 ma ( m in) and 4.5 ma ( m ax) , r set = 5.1 k?
adf4151 data sheet rev. b | page 10 of 28 ?60 ?80 ?100 ?120 ?140 ?160 ?180 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) 10265-008 figure 8 . integer- n phase noise and spur performance; low noise mode; vco out = 1750 mhz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth = 50 khz ?60 ?80 ?100 ?120 ?140 ?160 ?180 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) 10265-009 figure 9 . fractional - n phase noise and spur performance; low noise mode; vco out = 1755.2 mhz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth = 50 khz, channel spacing = 200 khz, frac = 26, mod = 125 ?60 ?80 ?100 ?120 ?140 ?160 ?180 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) 10265-010 figure 10 . fractional - n phase noise and spur performance; low spur mode; vco out = 1755.2 mhz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth = 50 khz, channel spacing = 200 khz, frac = 26, mod = 125 ?60 ?80 ?100 ?120 ?140 ?160 ?180 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) 10265-011 figure 11 . integ er- n phase noise and spur performance; low noise mode; vco out = 900 mhz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth = 20 khz ?60 ?80 ?100 ?120 ?140 ?160 ?180 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) 10265-012 figure 12 . fractional - n phase noise and spur performance; low noise mode; vco out = 905.2 m hz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth= 20 khz , channel spacing = 200 khz, frac = 26, mod = 125 ?60 ?80 ?100 ?120 ?140 ?160 ?180 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) 10265-013 figure 13 . fractional - n phase noise and spur performance; low spur mode; vco out = 905.2 mhz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth = 20 khz, channel spacing = 200 khz, frac = 26, mod = 125
data sheet adf4151 rev. b | page 11 of 28 circuit description reference input sect ion the reference input stage is shown in figure 14 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power - d own is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power - down. buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control 10265-014 figure 14 . reference input stage rf n divider the rf n divider a llows a division ratio in the pll feedback path . division ratio is determined by the in t, f rac , and mod values, which build up this divider . int, frac, mod , and r counter relationship the int, frac, and mod values, in conjunc tion with the r counter, make i t possible to generate output frequencies that are spaced by f ractions of the pfd frequency . see the rf synthesizer a worked example section for more information. the rf vco frequency (rf out ) equation is rf out = f pfd ( int + ( f rac / mod )) (1) w here : rf out is the output frequency of the external voltage controlled oscillator (vco). int is the preset divide ratio of the binary 16 - bit counter (23 to 32,767 for 4/5 prescaler, 75 to 65 , 535 for 8/9 prescaler). frac is the numerator of the fractional division (0 to mod ? 1). mod is the preset fractional modulus ( 2 to 4095 for low noise mode, 50 to 4095 for low spur mode ). f pfd = ref in [(1 + d)/(r (1 + t))] (2) where : ref in is the reference input frequency. d is the ref in doubler bit . r is the preset divide ratio of the binary 10 C bit programmable reference counter (1 to 1023). t is the ref in divide - by - 2 bit (0 or 1). third-order fractional interpolator frac value mod reg int reg rf n divider n = int + frac/mod from vco output/ output dividers to pfd n counter 10265-015 figure 15 . rf int divider int n m ode if the frac = 0 and db8 in register 2 (ldf) is set to 1 , the synthesizer operates in integer - n mode. the db8 in register 2 (ldf) should be set to 1 to get integer - n digital lock detect. additionally, lower phas e noise is possible if the anti backlash pulse width is reduced to 3 ns. this mode is not valid for fr actional - n applications . r counter the 10 - bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 1023 are allowed. phase frequency dete ctor (pfd) and charge pump t he p hase f requency d etector ( pfd ) takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 16 is a simplified schematic of the phase frequency de t ector. the pfd includes a programmable delay element that sets the width of the anti backlash pulse, which can be either 6 ns (default , for fractional - n applications ) or 3 ns (for integer - n mode) . this pulse ensures that there is no dead zone in the pfd tra nsfer function and gives a consistent reference spur level. u3 clr2 q2 d2 u2 down up high high cp ?in +in charge pump delay clr1 q1 d1 u1 10265-016 figure 16 . pfd simplified schematic
adf4151 data sheet rev. b | page 12 of 28 muxout and lock detect the output multiplexer on the adf4151 allows the user to acce ss various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 (for details, see figure 21 ). figure 17 shows the muxout section in block diagram form. d gnd dv dd control mux muxout analog lock detect digital lock detect r counter output n counter output dgnd reserved three-state-output dv dd r counter input 10265-017 figure 17 . muxout schematic input shift register s the adf4151 digital section includes a 10 - bit rf r counter, a 16 - bit rf n counter, a 12 - bit frac counter, and a 12 - bit modulus counter. data is clocked into the 32 - bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of six latches on the rising edge of le. the destination latch is determined by the state of the three control bits (c3, c2 , and c1) in the shift register. there are three lsbs : db2, db1, and db0, as shown in figure 2 . the truth table for these bits is shown in table 5 . figure 18 shows a su mmary of how the latches are programmed. table 5 . c3, c2, and c1 truth table control bits c3 c2 c1 register 0 0 0 register 0 (r0) 0 0 1 register 1 (r1) 0 1 0 register 2 (r2) 0 1 1 register 3 (r3) 1 0 0 register 4 (r4) 1 0 1 register 5 (r5) program modes figure 19 through figure 24 show how the program modes are to be set up in the adf4151 . a number of settings in the adf4151 are double buffered. these include the modulus value, phase value, r counter value, reference doubler, reference divide - by - 2, and current setting. this means that two events must occur before the part uses a new value of any of the double - buffered settings. first, the new value is latched into the device by writing to the appropriate register. second, a new writ e must be performed on register r0. for example, any time the modulus value is updated, register r0 must be written to, t hus ensur ing that the modulus value is loaded correctly.
data sheet adf4151 rev. b | page 13 of 28 register maps db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 ph1 pr1 p12 p11 p10 p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 0 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(0) c2(1) c1(0) csr rdiv2 reference doubler charge pump current setting 10-bit r counter control bits db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 f3 f2 0 0 f1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value ldp pd polarity power-down cp three- state counter reset clk div mode dbr 1 1 dbr = double buffered register?buffered by the write to register 0. reserved ldf reserved abp charge cancel reserved register 4 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(0) control bits reserved ld pin mode register 0 register 1 register 2 register 3 register 5 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d15 d14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(1) control bits reserved reserved reserved db r 1 dbr 1 dbr 1 dbr 1 dbr 1 reserved prescaler low noise and low spur modes muxout phase adjust reserved 10265-018 figure 18 . register summary
adf4151 data sheet rev. b | page 14 of 28 n16 n15 ... n5 n4 n3 n2 n1 integer value (int) 0 0 ... 0 0 0 0 0 not allowed 0 0 ... 0 0 0 0 1 not allowed 0 0 ... 0 0 0 1 0 not allowed . . ... . . . . . ... 0 0 ... 1 0 1 1 0 not allowed 0 0 ... 1 0 1 1 1 23 0 0 ... 1 1 0 0 0 24 . . ... . . . . . ... 1 1 ... 1 1 1 0 1 65533 1 1 ... 1 1 1 1 0 65534 1 1 ... 1 1 1 1 1 65535 f12 f11 .......... f2 f1 fractional value (frac) 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 ......... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) intmin = 75 with prescaler = 8/9 10265-019 figure 19 . register 0 (r0) p12 p11 .......... p2 p1 phase value (phase) 0 0 .......... 0 0 0 0 0 .......... 0 1 1 (recommended) 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 ph1 pr1 p12 p11 p10 p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) reserved m12 m11 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... m2 m1 interpolator modulus (mod) 0 0 1 0 2 0 0 1 1 3 . . . . . . . . . . . . . . . 1 1 0 0 4092 1 1 0 1 4093 1 1 1 0 4094 1 1 1 1 4095 prescaler phase adjust p1 prescaler 0 4/5 1 8/9 ph1 phase adjust 0 off 1 on db r db r 10265-020 figure 20 . registe r 1 (r1)
data sheet adf4151 rev. b | page 15 of 28 rd2 reference doubler 0 disabled 1 enabled rd1 reference divide by 2 0 disabled 1 enabled c p4 c p3 c p2 c p1 i cp (ma) 5.1k? 0 0 0 0 0.28 0 0 0 1 0.56 0 0 1 0 0.84 0 0 1 1 1.13 0 1 0 0 1.41 0 1 0 1 1.69 0 1 1 0 1.97 0 1 1 1 2.25 1 0 0 0 2.53 1 0 0 1 2.81 1 0 1 0 3.09 1 0 1 1 3.38 1 1 0 0 3.66 1 1 0 1 3.94 1 1 1 0 4.22 1 1 1 1 4.5 r10 r9 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... r2 r1 r divider ( r ) 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 1020 1 1 0 1 1021 1 1 1 0 1022 1 1 1 1 1023 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 0 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(0) c2(1) c1(0) rdiv2 dbr reference doubler dbr charge pump current setting 10-bit r counter dbr control bits ldp pd polarity power-down cp three- state counter reset ldf muxout reserved u5 ldp 0 10ns 1 6ns u4 pd polarity 0 negative 1 positive u3 power-down 0 disabled 1 enabled u2 cp three-state 0 disabled 1 enabled u1 counter reset 0 disabled 1 enabled u6 ldf 0 frac-n 1 int-n reserved m3 m2 m1 output 0 0 0 three-state output 0 0 1 dv dd 0 1 0 dgnd 0 1 1 r divider output 1 0 0 n divider output 1 0 1 analog lock detect 1 1 0 digital lock detect 1 1 1 reserved l1 l2 noise mode 0 0 low noise mode 0 1 reserved 1 0 reserved 1 1 low spur mode low noise and low spur modes 10265-021 figure 21 . register 2 (r2)
adf4151 data sheet rev. b | page 1 6 of 28 c 2 c 1 clock divider mode 0 0 clock divider off 0 1 fast lock enable 1 0 resync enable 1 1 reserved d12 d11 .......... d2 d1 clock divider value 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 csr db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 f1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value clk div mode reserved f1 cycle slip reduction 0 disabled 1 enabled reserved 0 0 reserved f 3 f 2 f 2 char g e canc e ll a t io n 0 d i s ab l e d 1 e nab l e d f 3 an t i back l a s h p u l se w i d t h 0 6 n s ( f rac - n ) 1 3 n s ( i n t _ n ) charge cancel abp 10265-022 figure 22 . register 3 (r3) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(0) control bits reserved 10265-023 figure 23 . register 4 (r4) ld pin mode db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d15 d14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(1) control bits reserved reserved d1 5 d1 4 lock detect pin operation 0 0 low 0 1 digital lock detect 1 0 low 1 1 high 10265-024 figure 24 . register 5 (r5)
data sheet adf4151 rev. b | page 17 of 28 r egister 0 control b its with bits [c3:c1] set to 0, 0 , 0 , r egister 0 is programmed. figure 19 shows the input data format for programming this register. 16- bit integer value (int) these 16 bits set the int value, which determine s the integer part of the feedback division factor. they are used in equation 1 (see th e int, frac, mod, and r counter relationship sectio n). all inte ger values from 23 to 32 , 767 are allowed for 4/5 prescal er. for 8/9 prescaler , the minimum integer v alue is 75 , and the max imum value is 65,535 . 12- bit fractional value (frac) the 12 frac bits set the numerator of the fraction that is input to the - modulator. this, along with int, specifies the new frequency channel that the synthesizer locks to, as shown in the rf synthesizer a worked example section . frac values from 0 to mod ? 1 cover channels over a frequency range equal to the pfd reference frequency. r egister 1 control bits with bits [ c3 :c1] set to 0, 0 , 1, r egister 1 is programmed. figure 20 shows the input data format for programming this register. phase adjust the phase adjust bit, enabled by programming a 1 to db28, permits adjustments to the output phase of a given output frequency. if enab led, it does not perform a phase resync function on updating r0. if se t to 0 , the phase resync (if enabled in r3 , bits[db16:db15] ) occur s on every update of r0. prescaler value the dual modulus prescaler (p/p + 1), along with the int, frac, and mod count ers, determines the overall division ratio from the vco output to the pfd input. operating at cml levels, it takes the clock from the vco output and divides it down for the counters. it is based on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 3 ghz. therefore, when operating the adf4151 above 3 ghz, this must be set to 8/9. the prescaler limits the int value , where : p = 4/5, n min = 23 p = 8/9, n min = 75 in the adf4151 , p r 1 in r egister 1 set s the prescaler values. 12- bit p hase value (phase) these bits control what is loaded as the phase word. the word must be less than t he mod value programmed in r egister 1 . the word is used to prog ram the rf output phase from 0 to 360 with a resolution of 360 /mod. see the phase resync section for more information. in most applications, the phase relationship between the rf signal and the reference is not impor tant. in such applications, the phase value can be used to optimize the fractional and subfractional spur levels. see the spur consistency and fractional spur optimization section for more information. if neither the phase resync nor the spu rious optimization functions are being used, it is recommended that the phase word be set to 1. 12- bit m odulus value (mod) this programmable register sets the fractional modulus. this is the ratio of the pfd frequency to the channel step resolution on the rf output. see the rf synthesizer a worked example section for more information. r egister 2 control b its with bits[c3: c1] set to 0 , 1, 0 , r egister 2 is programmed. figure 21 shows the input data format f or programming this register. low noise and spur mode s the noise modes on the adf4151 are con trolled by db30 and db29 in r egister 2 ( s ee figure 21) . the noise modes allow the user to optimize a design either for improved spurious perfor - mance or for improved phase noise performance. when the lowest spur setting is chosen, dither is enabled. this randomizes the fr actional quantization noise so it resembles white noise rather than spur ious noise. as a result, the part is optimized for improved spurious performance. this operation would normally be used when the pll closed - loop bandwidth is wide, for fast locking applications. (wide - loop bandwidth is seen as a loop bandwidth greater than 1/10 of the rf out channel step resolution (f res )). a wide loop filter does not attenuate the spurs to the same level as a narrow - loop bandwidth. for best noise performance, use the lowest noise setting option. as well as disabling the dither, it also ens ures that the charge pump is operating in an optimum region for noise performance . this setting is extremely useful where a narrow - loop filter band width is available. the synthesizer ensures extremely low noise , and the filter attenuates the spurs. the typ ical p erformance characteristics give the user an idea of the trade - off in a typical w - cdma setup for the different noise and spur settings.
adf4151 data sheet rev. b | page 18 of 28 muxout the on - chip multiplexer is controlled by bits [db28: db26 ] ( s ee figure 21) . referen ce doubler setting db25 to 0 feeds the ref in signal directly to the 10 - bit r counter, disabling the doubler. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 10- bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and the lowest spur mode is chos en, the in - band phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for the ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cycle in the lowest nois e mode. the phase noise is insensitive to the ref in duty cycle when the doubler is disabled. when the doubler is enabled, t he maximum allowable ref in frequency is 30 mhz. rdiv 2 setting the db24 bit to 1 inserts a divide - by - 2 toggle flip - flop between the r counter and pfd, which extends the maximum refin input rate. this function allows a 50% duty cycle signal to appear at the pfd input, which is necessary for cycle slip reduction. 10- bit r counter the 10 - bit r counter allows the input reference frequency ( ref in ) to be divided down to produce the reference clock to the pfd . division ratios from 1 to 1023 are allowed. current setting bits[ db12 :db 9 ] set the charge pump current setting. this should be set to the charge pump current that the loop filter is desi gned with (see figure 21). ldf setting db 8 to 1 enables integer - n digital lock detect , when the frac part of the divider is zero; setting db8 to 0 enables fractional - n digital lock detect . lock detect precision (ldp) when db7 is set to 0, the fractional - n digital lock detect is activated. in this case after setting db7 to 0, 40 consecutive pfd cycles of 10 ns must occur before digital lock detect is set. when db7 is programmed to 1, 40 consecutive reference cycles of 6 ns must oc cur before digital lock detect goes high. setting db8 (ld f ) to 1 causes the activation of the integer - n digital lock detect. in this case, after setting db7 (ldp) to 0 , five consecutive cycles of 10 ns must occur before digital lock detect is set. when db7 is set to 1, five consecutive cycles of 6 ns must occur. r ecommended setting s of both the ldp and ldf bits are shown in table 6 . table 6 . recommended ldf/ldp bit s ettings mode db8 (ldf) db7 (ldp) integer -n 1 1 fractional - n low noise mode 0 1 fractional - n low spur mode 0 0 phase detector polarity db6 sets the phase detector polarity. when a passive loop filter or non inverting active loop filter i s used, set this bit to 1. if an active filter with an inv erting characteristic is used, this bit should be set to 0. power - down (pd) db5 provides the programmable power - down mode. setting this bit to 1 performs a power - down. setting this bit to 0 returns the synthesizer to normal operation. wh en in software powe r - down mode, the part retains all information in its registers. on ly if the supply voltages are removed are the register contents lost. when a power - down is activated, the following events occur: ? the synthesizer counters are forced to their load state cond itions. ? the charge pump is forced into three - state mode. ? the digital lock detect circuitry is reset. ? the rf out buffers are disabled . ? the input register remains active and capable of loading and latching data. charge pump (cp) three - state db4 puts the charg e pump into three - state mode when programmed to 1. it should be set to 0 for normal operation. counter reset db3 is the r counter and n counter reset bit for the adf4151 . when this bit is 1, the rf synthesizer n counter and r counter ar e held in reset. for normal operation, this bit should be set to 0.
data sheet adf4151 rev. b | page 19 of 28 r egister 3 control b its with bits [c3: c1] set to 0 , 1, 1 , r egister 3 is programmed. figure 22 shows the input data format for programmi ng this register. ant ib acklash pulse width setting db22 to 0 sets the pfd antibacklash pulse width to 6 ns. this is the recommen ded mode for fractional - n use. by s ettin g this bit to 1, the 3 ns pulse width is used and result s in a phase noise and spur imp rovement in integer - n operation. for fractional - n mode it is not recommended to use this smaller setting. charge cancellation mode pulse width setting db21 to 1 enables charge pump charge cancellation. this has the effect of reducing pfd spurs in integer - n mode. in fractional - n mode , this bit should not be used. this results in a phase noise and fractional spur improvement. cycle slip reduction ( csr ) enable setting db18 to 1 enables cycle slip reduction. this is a method for improving lock times. note tha t the signal at the phase fre - quency detector (pfd) must have a 50% duty cycle for cycle slip reduction to work. the charge pump current setting must also be set to a minimum. see the cycle slip reduction for faster lock times sec tion for more information. clock divider mode b its [db16: db15 ] must be set to 1, 0 to activat e phase r esync or 0, 1 to activ ate fast lock. setting bits[db16:db15] to 0, 0 disables the clock divider. see figure 22. 12- bit clock divi der value the 12 - bit clock divider value sets the timeout counter for activation of phase r esync. see th e phase resync section for more information. it also sets the timeout counter for fast lock. see t he fast lock timer and register sequences section for more information. r egister 4 control b its with bits[c3: c1] set to 1, 0, 0 , r egister 4 is programmed. figure 23 shows the input data format for programming this register. this r egister is reserved and has to be programmed with the values as shown in figure 23 . bits [db31:db24] and [db22:db3 ] must be programmed to 0, while b it db23 must be set to 1. r egister 5 control b its with bits[c3: c1] set to 1, 0, 1 , r egister 5 is programmed. figure 24 shows the input data form for programming this register. lock detect pin operation bits [db 2 3 : db22 ] set the o peration of the lock detect pin (s ee figure 24) . i nitializ ation s equence the following sequence of registers is the correct sequence for initial power up of the adf4151 after the correct application of voltages to the supply pins: 1. register 5 2. register 4 3. register 3 4. register 2 5. register 1 6. register 0
adf4151 data sheet rev. b | page 20 of 28 rf synthesizer a worked example the following is an example of how to program the adf4151 synthesizer: rf out = [ int + ( frac / mod )] [ f pfd ] / rf divider (3) where: rf out is the rf frequency output. int is the integer division factor. frac is the fractionality. mod is the modulus. rf divider is the output divider that divides down the vco frequency. f pfd = ref in [(1 + d) /( r (1 + t ))] (4) where: ref in is the reference frequency input. d is the rf ref in doubler bit. r is the rf reference division factor. t is the reference divide - by - 2 bit (0 or 1). for example, in a umts system, where 2112.6 mhz rf frequency output (rf out ) is required, a 10 mhz reference frequency input (ref in ) is available, and a 200 khz channel resolution (f resout ) is required on the rf output. a 2.1 ghz vco is suitable to cover the required fractional frequency of 2112.6 mhz. f pfd pfd vco n divider rf out 10265-025 figure 25 . loop closed before output divider a channel re solution ( f res ) of 200 khz is required at the output of the vco. mod = ref in / f res mod = 10 mhz / 2 00 khz = 5 0 from equation 4 f pfd = [10 mhz (1 + 0)/1] = 10 mhz (5) 2112.6 mhz = 10 mhz ( int + frac / 50) (6) where: int = 211 frac = 13 modulus the choice of modulus (mod) depends on the reference signal (ref in ) available and the channel resolution (f res ) required at the rf output. for example, a gsm system with 13 mhz ref in sets the modulus to 65. this means that the rf output resolution (f res ) is the 200 khz (13 mhz/65) necessary for gsm. with dither off, the fractional spur interval depend s on the modulus values chosen (s ee table 7 ). reference doubler an d reference divider the reference doubler on chip allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually improves noise performance by 3 db. it is important to note that the pfd cannot operate above maximum value (see table 1 ) due to a limitation in the speed of the - circuit of the n - divider. the reference divide - by - 2 divides the reference signal by 2, resulting in a 50% duty cycle pfd frequency. this is necessary for the correct operation of the cycle slip reduction (csr) f unction. see the cycle slip reduction for faster lock times s ection for more information. 12- bit programmable mod ulus unlike most other fractional - n plls, the adf4151 allows the user to program the modulus over a 12 - bit range. this means that the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 10 - bit r counter. for example , consider an application that req uires 1.75 ghz rf and 200 khz channel step resolution. the system has a 13 mhz reference signal. one possible setup is feeding the 13 mhz directly to the pfd and programming the modulus to divide by 65. this results in the required 200 khz resolution. anot her possible setup is using the reference doubler to create 26 mhz fr om the 13 mhz input signal. the 26 mhz is then fed into the pfd , programming the modulus to divide by 130. this also results in 200 khz resolution and offers superior phase noise performa nce over the previous setup. the programmable modulus is also very useful for multi - standard applications. if a dual - mode phone requires pdc and gsm 1800 standards, the programmable modulus is a great benefit. pdc requires 25 khz channel step resolution, whereas gsm 1800 requires 200 khz channel step resolution.
data sheet adf4151 rev. b | page 21 of 28 a 13 mhz reference signal can be fed directly to the pfd , and the modulus can be programmed to 520 when in pdc mode (13 mhz/520 = 25 khz). the modulus needs to be reprogrammed to 65 for gsm 180 0 operation (13 mhz/65 = 200 khz). it is important that the pfd frequency remain constant (13 mhz) . this allows the user to de sign one loop filter for both setups without running into stability issues. it is important to remem - ber that the ratio of the rf frequency t o the pfd frequency principally affects the loop filter design , not the actual channel spacing . cycle slip reduction for faster lock time s as outlined in the low noise and spur mode section, the adf4151 contains a number of features that allow optimization for nois e performance. however, in fast l ocking applications, the loop bandwidth generally needs to be wide, and , therefore, the filter does not provide much attenuati on of the spurs. if the cycle slip reduction feature is enabled , the narrow - loop ban dwidth is maintained for spur attenuation but fast er lock times are still possible . cycle slips cycle slips occur in integer - n/fractional - n synthesizers when the loop band width is narrow compared to the pfd frequency. the phase error at the pfd inputs accumulates too fast for the pll to correct, and the charge pump temporarily pumps in the wrong direction. this slows down the lock time dramatically. the adf4151 contain s a cycle slip reduction feature that extend s the linear range of the pfd , allowing faster lock tim es without modifications to the loop filter circuitry . when the circuitry detects that a cycle slip is about to oc cur, it turns on an extra charge pump current cell. this outputs a cons tant current to the loop filter or removes a constant current from the loop filter (depending on whether the vco tuning voltage needs to increase or decrease to acquire the new frequ ency). the effect is that the linear range of the pfd is increased. loop s tability is maintained because the current is constant and is not a pulsed current. if the phase error increases again to a point where another cycle slip is likely, the adf4151 turns on another charge pump cell. this continues until the adf4151 detects that the vco frequency has gone past the desired frequency. the extra charge pump cells are turned off one by one until all the extra charge pump cells have been disabled and the frequency is settled with the original loop filter bandwidth . up to seven extra charge pump cells can be turned on. in most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times. setting bit db18 in the r egister 3 to 1 enables cycle slip reduction. note that the pfd requires a 45% to 55% dut y cycle f or csr to operate correctly. spurious optimizatio n and fast lock narrow - loop b andwidths can filter unwanted s purious signals , but these usually have a long lock time. a wider loop bandwidth achieve s fast er lock times, but a wider loop bandwidth may lead to increased spurious signals inside the loop bandwidth . t he fast lock feature c an achieve the same fast lock tim e as the wider bandwidth , but with the advantage o f a narrow final loop bandwidth to keep spurs low . fast lock timer and regis ter sequences if the fast lock mode is used, a timer value must be loaded into the pl l to determi ne the duration of the wide bandwidth mode. when bits [db16: db15 ] in r egister 3 are set to 0, 1 (fast lock enable), the timer value is loaded by the 12 - bit clock divider value. t he following sequence must be programmed to use fast lock : 1. initialization s e quence ( s ee the initialization sequence section ); occurs only once after powering up the part. 2. load r egister 3 by setting bits [db16: db15 ] to 0, 1 and the cho sen fast lock timer value , bits [db14:db3] . note that the length of time the pll remains in wide bandwidth is equal to the fast lock timer/f pfd .
adf4151 data sheet rev. b | page 22 of 28 fast lock an example if a pll has a reference frequency of 13 mhz , a f pfd of 13 mhz and a required lock time of 50 s, the pll is set to wide bandwidth for 40 s. this example assumes a modulus of 65 for channel spacing of 200 khz. if the time period set for the wide bandwidth is 40 s, then fast lock timer value = time in wide bandwidth f pfd / mod fast lock timer value = 40 s 13 mhz / 65 = 8 therefore, 8 must be loaded into the clock d ivider value in r egister 3 in step 1 of the sequence described in the fast lock timer and register sequences section. fast lock loop filter topology t o use fast lock mode, t he damping resistor in the loop filter is reduced to ? o f its value while in wide bandwidth mode. to achieve the wider loop filter bandwidth, the charge pump current increases by a factor of 16. t o maintain loop stability , the damping resistor must be reduced a factor of ? . to enable fast lock, the sw pin is sh orted to the gnd pin by setting b its [db16: db15 ] in register 3 to values 0, 1 . the following two t opologies are available : ? t he damping resistor (r1) is divided into two values (r1 and r1a) that have a ratio of 1:3 (see figure 26). ? a n extra resistor (r1a) is connected directly from sw, as shown in figure 27 . the extra resistor is calculated such that the parallel combination of an extra resistor and the damping resistor (r1) is reduced to ? of the origi nal value of r1 (see figure 27). adf4151 cp out sw c1 c2 r2 r1 r1a c3 vco 10265-026 figure 26 . fast lock loop filter topology topology 1 adf4151 cp out sw c1 c2 r2 r1 r1a c3 vco 10265-027 figure 27 . fast lock loop filter topology topology 2 spur mechanisms this section descr ibes the three different spur mechanisms that arise with a fractional - n synthesizer and how to minimize them in the adf4151 . fractional spurs the fractional interpolator in the adf4151 is a third - order - modulato r (sdm) with a modulus (mod) that is programmable to any integer value from 2 to 4095. in low spur mode (dither enabled) , the minimum allowable value of mod is 50. the sdm is clocked at the pfd reference rate (f pfd ) that allows pll output frequencies to be synthesized at a channel step resolution of f pfd /mod . in low noise mode (dither off ), the quantization noise from the - modulator appears as fractional spurs. the interval between spurs is f pfd /l, where l is the repeat length of the c ode sequence in the digital - modulator. for the third - order modulator used in the adf4151 , the repeat length depends on the value of mod, as listed in table 7 . table 7 . fractional spurs with dither off condition (dither off) repeat length spur interval if mod is divisible by 2, but not 3 2 mod channel step/2 if mod is divisible by 3, but not 2 3 mod channel step/3 if mod is divisible by 6 6 mod channel step/6 otherwise mod channel step in low spur mode (dither on ), the repeat length is extended to 2 21 cycles, regardless of the value of mod, which makes the quantization error spectrum look like broadband noise. this may degrade the in - band phase noise at the pll output by as much as 10 db. f or lowest noise, dither off is a better choice, particularly when the final loop bandwidth is low enough to attenuate even the lowest frequency fractional spur. integer boundary spurs another mechanism for fractiona l spur creation is the interactions between the rf vco frequency and the reference frequency. when these frequencies are not integer related (the point of a fractional - n synthesizer) spur sidebands appear on the vco output spectrum at an offset frequency t hat corresponds to the beat note or difference frequency between an integer multiple of the refere nce and the vco frequency. these spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency c an be inside the loop bandwidth; therefore , the name integer boundary spurs.
data sheet adf4151 rev. b | page 23 of 28 reference spurs reference spurs are generally not a problem in fractional - n synthesizers because the reference offset is far outside the loop bandwidth . how ever, any reference feed through mechanism that bypasses the loop can cause a prob lem. f eed through of low levels of on - ch ip reference switching noise, through the rf in pin back to the vco, can result in reference spur levels as high as ? 90 dbc. pcb la yout must ensure adequate isolation between vco traces and the input ref erence to avoid a possible feed through path on the board. spur consistency and fractional spur optimization with dither off, the fractional spur pattern due to the quanti - zation noise of the sdm also depends on the particular phase word with which the modulator is seeded. the phase word can be varied to optimize the fractional and subfractional spur levels on any particular frequency. thus, a look - up table of phase values corresponding to each frequency can be constructed for use when programming the adf4151 . if a look - up table is not used, keep the phase word at a constant value to ensure consistent spur levels on any particular frequency . p hase r esync the output of a fractional - n pll can settle to any one of the mod phase offsets with respect to the input reference, where mod is the fractional modulus. the phase resync feature in the adf4151 p roduce s a consistent output phase offset with respect to the input reference. this is necessary in applications where the output phase and frequency are important, such a s digital beam forming. see the phase programmability se ction for how to program a specific rf output phase when using phase resync. phase resync is enabled by setting bit db16 , bit db15 i n register 3 to 1, 0 . when phase resync is enabled, an internal timer generates sync signals at intervals of t sync given by the following formula: t sync = clk_div_value mod t pfd w here : clk_div_value is the decim al value programmed in bits [ db 14: db 3] of register 3 and can be any integer in the range of 1 to 4095. mod is the modulus value pr ogrammed in bit s [ db 14: db 3] of regi ster 1 (r1). t pfd is the pfd reference period. when a new frequency is programmed, the second sync pulse after the le rising edge is used to resynchronize the output phase to the reference. the t sync time must be programmed to a value that is a t least as long as the worst - case lock time. this guarantees that the phase resync occurs after the last cycle slip in the pll settling transient. in the example shown in figure 28 , the pfd reference is 25 mhz and mod is 125 for a 200 khz channel spacing. t sync is set to 400 s by programming the clock divider value, clk_div_value , to 80. 10265-028 l e pha se f r eq u enc y syn c (i n t erna l ) ?10 0 0 10 0 20 0 100 0 30 0 40 0 50 0 60 0 70 0 80 0 90 0 t i me ( s ) pll settl es t o c o rr ec t pha se a fter r esy n c t sy n c l a st c yc l e sl i p pll settl es t o i nc o rr ec t pha se figure 28 . phase resync example p hase programmability the phase word in register 1 controls the rf output phase . as this word is swept from 0 to mod, the rf output phase sweeps over a 360 range in steps of 360 /mod.
adf4151 data sheet rev. b | page 24 of 28 applications informa tion direct conversion mo dulator direct conversion architectures are increasingly being used to implement base station transmitters. figure 29 shows how analog devices, inc., parts can be used to implement such a system . the circuit block diagram shows the ad9788 txdac? being used with the adl5375 . the use of dual integrated dacs, such as the ad9788 with its specified 0.02 db and 0.004 db gain and offset matching characteristics, ensures minimum error contrib ution (over temp erature) from this portion of the signal chain. the signal for the i channel of the quadrature modulat or is taken from the out1 differential output s of the ad9788 , and the out2 differential outputs provide the signal for the q channel of the quadrature modulator adl5375 . the local oscillator (lo) is implemented using the adf4151 . t he low - pass filter was designed using adisimpll? for a channel spacing of 200 khz and a closed - loop bandwidth of 35 khz . the lo ports of the adl5375 can be driven from the vco output . to ensure that all three rf ports ( vco output, rf in and loip ) are connected to 5 0 ? impedance , the matching network of three 18 ? resistors must be placed as in figure 29. ac coupling of the rf signal is implemented by the capacitors connected in serial with the 18 ? resistors . it is po ssible , as well , to use a balun to convert from a single - ended lo input to the differential lo inputs for the adl5375 . if the i and q inputs are driven in quadrature by 2 v p - p signals, the resulting output p ower from the modulator is approximately 2 dbm. 10265-029 ad9788 txdac refio fsadj out2_n out1_p out1_n out2_p 2k? low-pass filter low-pass filter 2700pf 1200pf 39nf 680 ? 360 ? ibbp ibbn qbbp qbbn loip loin spi-compatible serial bus adf4151 cp gnd a gnd a gnd sd gnd 1nf 1nf 4.7k? r set le data clk ref in fref in cp out av dd 2 av dd 2 ce muxout v cc vco out vco v tune 17 16 av dd 1 10 29 1 2 3 22 8 11 18 31 v dd lock detect 51? 51? 51? 51? 51? 25 30 ld 7 d vdd 28 32 6 sdv dd v p 5 sw 4 adl5375 rfout quadrature phase splitter ds op rf in? rf in+ 15 14 1nf 1nf 100pf 100pf v vco 18? 100pf 18? 18? modulated digital data v p 9 a gnd a gnd 21 d gnd 27 d gnd 26 figure 29 . direct conversion modulator
data sheet adf4151 rev. b | page 25 of 28 interfacing the adf4151 has a simple s pi - compatible serial interface for writing to the device. clk, data, and le control the data transfer. when le goes high, the 32 bits that have been clocked into the appropriate register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the t iming diag ram and table 5 fo r the register address table. aduc812 interface figure 30 shows the interface between the adf4151 and the aduc812 microconverter?. because the aduc812 is based on an 8051 core, this interface can be used with any 8051 - based microcontroller. the microconverter is set up for spi master mode w ith cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4151 needs a 32- bit word, which is accomplished by writing four 8 - bit bytes from the microconverter to the device. when the fourth byte has been written, the le input should be brought high to complete the transfer. aduc812 adf4151 clk data le ce muxout (lock detect) sclock mosi i/o ports 10265-030 figure 30 . aduc812 to adf41 51 interface i/o port lines on the aduc812 are also used to control power - down (ce input) and detect lock (muxout configured as lock detect and polled by the port input). when operating in the described mod e, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 125 khz. blackfin bf527 interface figure 31 shows the interface between the adf4151 and the blackfin adsp - bf527 digital signal processor (dsp). the adf4151 needs a 32 - bit serial word for each latch write. the easiest way to accomplish this using the blackfi n family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use four memory locatio ns for each 32- bit word. to program each 32 - bit latch, store the four 8 - bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. as in the microcontroller case , just mak e sure that the clock speeds are within the maximum limits outlined in table 2 . adsp-bf527 adf4151 clk data le ce muxout (lock detect) sclk mosi gpio i/o flags 10265-031 figure 31 . adsp - bf527 to adf4151 interface pcb design guideline s for chip scale package the lands on the chip scale pa ckage (cp - 32- 7 ) are rectangu lar. the pcb pad for these must be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land is to be centered on the pad. this ensures that t he solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the pcb must be at least as large as the exposed pad. on the pcb, there is to be a minimum clearance of 0.25 mm between the thermal pad an d the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, they are to be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with one ounce copper to plug the via.
adf4151 data sheet rev. b | page 26 of 28 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 32 . 32 - lead lead frame chip scale package [lfcsp_ w q] 5 mm 5 mm bo dy, very thin quad (cp - 32 - 7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adf4151 bcpz ? 40c to +85c 32- lead lead f rame chip scale package [lfcsp_w q] cp -32-7 adf4151 bcpz - rl7 ?40c to +85c 32- lead lead frame chip scale package [lfcsp_wq] cp -32-7 eval - adf4151 eb1z evaluation board 1 z = rohs compliant part.
data sheet adf4151 rev. b | page 27 of 28 notes
adf4151 data sheet rev. b | page 28 of 28 notes ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d1026 5- 0- 12/11(b)

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